TSMC CoWoS Capacity Allocation Update: 190–200kwpm Consensus, AMD 355k–540k, and the Debate Over 50–80kwpm of External Capacity
目录
TL;DR
1. First Split the Eight Brokers Into Three Different Scopes; 190–200kwpm Is the Real Consensus
JPMorgan, Morgan Stanley, and Goldman Sachs Are All Revising Up
II. 240 kwpm Is Still Tight; the Shortage Is Embedded in Full-Year Effective Output
III. NVIDIA at About 1.2 Million Wafers; Supply-Chain Consensus Is Already Strong
IV. AMD’s Comparable Gap Is 185k Wafers, About Two-Thirds Explained by Venice
V. ASIC Direction Is Consistent, but AWS and Packaging Routes Still Diverge
VI. SoIC Moves to 2028, CoPoS Volume Production Lands in 2029
VII. Profit Ranking: TSMC Gets Certainty, OSAT Gets Verification Upside
VIII. Three Scenarios and Verification Over the Next Four Quarters
IX. Conclusion: The Firmest Consensus Is at TSMC; the Largest Return Dispersion Is in OSAT
本内容基于公开资料和研报数据整理，不构成任何投资建议，不代表任何个人观点，仅供学习参考，请理性阅读
After incorporating Goldman Sachs, UBS, BofA, Nomura, Citi, and HSBC, 190–200kwpm remains the latest single-company consensus for TSMC, while the global view is 210–280kwpm. The gap mainly reflects differences in dates, WMCM, CoW, and OSAT boundaries; profit spillover depends on whether 50–105kwpm of external nominal capacity can become qualified delivery.
TL;DR
190–200kwpm remains the latest direct consensus. UBS put TSMC at 150kwpm on May 21, BofA at 180kwpm on June 24, JPMorgan at 190kwpm on July 10, and Morgan Stanley at 200kwpm on July 8. These four figures carry different dates and should not be treated as four same-day forecasts; the two most recent direct estimates differ by only 5%.
The comparable range for global supply is 210–280kwpm. UBS, JPMorgan, BofA, and Morgan Stanley put 2027 year-end global or industry capacity at 210, 240, 275, and 280kwpm, respectively. Goldman Sachs also gives 280kwpm, but it includes WMCM; this indicates broader TSMC back-end space and should not be mixed into a pure CoWoS high-low ranking.
Sell-side forecasts are converging upward. JPMorgan raised its 2027 year-end TSMC capacity estimate from 155kwpm in April to 190kwpm in July, while Morgan Stanley raised its estimate from 165kwpm to 200kwpm in late May and has maintained it since. Goldman Sachs also raised its 2027 annual capacity including WMCM from 2,490k to 2,730k; the directional message is more consistent than the static high-low comparison.
The external capacity range has widened to 50–105kwpm. JPMorgan assigns 50kwpm to OSATs, UBS 60kwpm, Morgan Stanley 80kwpm but includes UMC, while BofA splits ASE Technology Holding and Amkor into 95–105kwpm. The wider range comes from statistical boundaries and report timing; ASE Technology Holding and Amkor’s yield and customer qualification will determine the extent of profit spillover.
AMD-related demand falls in the 355k–540k wafer range. After standardizing the Xilinx classification, Morgan Stanley remains clearly above JPMorgan, with Venice CPU the largest single source of difference. The key follow-ups are actual Venice shipments, MI455/MI450 customer pull-ins, and whether AMD cuts bookings again; these will determine whether the high-case scenario holds.
CPUs are reshaping the advanced-packaging division of labor. In 2027, Vera is about 5 million units and Venice about 3.2 million–6 million units, as server CPUs begin adopting 2.5D advanced packaging at scale. TSMC is prioritizing large-area CoWoS-L accelerators, with more CPUs handed to ASE Technology Holding and Amkor. Multiple brokers recognize this division of labor, with disagreements concentrated on CPU volume and OSAT yield.
SoIC and CoPoS will not release supply immediately. JPMorgan believes 50%–60% of AP7 Phase 2 resources have already been shifted to CoWoS, while SoIC year-end capacity does not rise to 65kwpm until 2028; CoPoS is expected to enter risk production in 2028 and mass production in 2029. Intel EMIB-T can absorb some TPU projects, but with around 60% substrate-level yield and uncertainty over subsequent customers, it can only provide partial relief for now.
1. First Split the Eight Brokers Into Three Different Scopes; 190–200kwpm Is the Real Consensus
After recent broker reports are put on the same basis, the capacity divergence has a clear hierarchy. The first layer is TSMC standalone, where the two most recent direct estimates land at 190–200kwpm; the second layer is TSMC plus external supply, which reaches 210–280kwpm by end-2027; the third layer is customer allocation, where HSBC assigns 480k wafers to Broadcom. Such numbers explain demand, but cannot be included in total capacity rankings.
The annual basis also needs to be separated. Nomura lists full CoWoS output and CoW front-end targets separately, while Citi’s historical benchmark and JPMorgan’s latest report both point to about 2,000k for the full year. Effective output on a narrow basis is roughly 1.85 million–2.00 million. Goldman Sachs’ 2,730k includes WMCM, reflecting broader back-end capability, and cannot be used to prove that pure CoWoS is 40% higher than other brokers’ estimates.
This table should not be ranked mechanically by number. The newer the report, the stronger the CPU and ASIC pull-ins visible to the broker; the broader the range, the easier it is to include WMCM, CoW front-end, or external CoWoS-like 2.5D packaging. There are only two comparable conclusions: the latest TSMC standalone estimates have moved close to 190–200kwpm, and global supply still needs more than 50kwpm of external capability to meet demand.
JPMorgan, Morgan Stanley, and Goldman Sachs Are All Revising Up
Cross-sectional comparison answers “what each broker thinks now”; the timeline answers “where the supply chain is moving.” All three brokers have pushed up their 2027 forecasts, making 190–200kwpm look more like the new TSMC standalone anchor than a coincidence across two reports.
The eight brokers provide total-volume boundaries, while the two July reports further break down customers and quarters. Morgan Stanley listed 2027 customer allocations on July 8, 2026; JPMorgan added the quarterly capacity paths for TSMC, OSATs, SoIC, and CoPoS on July 10. Putting the two tables together lets us map certainty and optionality to specific customers.
Certainty comes from two numbers. TSMC’s 2027 year-end in-house CoWoS capacity is 190–200kwpm, and Nvidia’s annual consumption is 1,196k–1,222k wafers. The error bands on both are small, indicating strong supply-chain consensus around the largest fab and the largest customer.
The optionality is concentrated in three areas. Morgan Stanley’s year-end non-TSMC capacity is superficially 30kwpm higher than JPMorgan’s OSAT scope; after standardizing the Xilinx classification, Morgan Stanley’s AMD-related demand is 185k wafers above JPMorgan’s; the two brokers also classify AWS and some custom chips differently. These gaps directly determine the revenue slope for ASE Technology Holding, Amkor, Alchip, Marvell Technology, and related substrate and testing companies.
The scope boundaries must be stated first. Annual consumption is k wafers/year, while capacity is kwpm or kwfpm, representing nominal monthly capacity; year-end monthly capacity cannot simply be multiplied by 12 and treated as full-year effective supply. JPMorgan’s table also notes that customer allocations are not yield-adjusted, while Morgan Stanley’s high-level customer table and product-detail table have a 30k gap; total demand should therefore be presented as a range.
II. 240 kwpm Is Still Tight; the Shortage Is Embedded in Full-Year Effective Output
J.P. Morgan raised its estimate for TSMC’s CoWoS capacity at end-2027 to 190 kwpm and OSAT capacity to 50 kwpm, for a combined 240 kwpm. It also said the near-term supply-demand gap has widened to roughly 20%, an institutional estimate. Both statements can be true, because 240 kwpm only represents nominal capacity at the end of the fourth quarter.
J.P. Morgan’s quarterly path better explains the pressure. TSMC rises from 130 kwpm in 1Q27 to 157, 175, and 190 kwpm by quarter, while OSAT rises from 22 kwpm to 30, 40, and 50 kwpm. A simple annualized stress test using average quarter-end nominal capacity is about 2,382k wafers, which is not the same as actual full-year output. The customer allocation table implies full-year demand of 2,381k wafers, leaving almost no nominal surplus.
A normal manufacturing system needs buffers for maintenance, line changeovers, yield, substrate shortages, and new-product ramp. Rubin Ultra uses dual dies; high-end Feynman versions may reach 9-10x reticle size; MI500 is more likely to reach 14-15x. The packaging area and process time consumed by the same chip continue to rise, making nominal wafer counts an increasingly weak proxy for real delivery capacity.
Including other institutions, external nominal capacity expands from 50 kwpm to around 105 kwpm. J.P. Morgan assigns OSAT 50 kwpm; UBS assigns 60 kwpm; Morgan Stanley assigns 80 kwpm but includes UMC; Bank of America separates ASE Technology Holding and Amkor at 70-75 kwpm and 25-30 kwpm, respectively. These numbers reflect different statistical boundaries and expansion assumptions, and cannot be treated as a like-for-like ranking.
Morgan Stanley’s supply assumption is wider. It expects TSMC at 200 kwpm and non-TSMC at 80 kwpm by end-2027. Its chart combines Amkor, UMC, and ASE Technology Holding, but does not disclose a company-by-company breakdown. J.P. Morgan assigns OSAT CoWoS-like capacity of 50 kwpm. The 30 kwpm difference can only be viewed as a headline gap; the confirmable disagreement lies in the speed of external outsourcing and effective yield.
At the same time, OSAT capacity expansion for CoWoS-like processes is picking up momentum, and we expect OSATs CoWoS-like capacity to reach 15k/50k/85k wfpm by end 26/27/28. Bulk of OSAT capacity is likely to be deployed for server CPU packaging, followed by networking and small volumes for accelerator chips such as LPU or Trainium 3. Overall, the demand-supply gap has recently expanded to ~20%, given the meaningful upside from agentic AI CPU demand.
TSMC is reallocating back-end space. J.P. Morgan believes AP7 Phase 2 was originally planned entirely for SoIC, but about 50%-60% has now been shifted to CoWoS. Some interposer wafer manufacturing is being selectively outsourced to Vanguard International Semiconductor, and CoWoS-R is expanding again. TSMC is retaining large-area, high-complexity accelerators, while CPUs, networking chips, and small volumes of accelerators are moving more to OSATs. This is a clear division of profit pools.
III. NVIDIA at About 1.2 Million Wafers; Supply-Chain Consensus Is Already Strong
NVIDIA is the most stable anchor across the two reports. Both forecasts land at around 1.2 million wafers, with TSMC handling close to 90% and the remainder mainly shared by external manufacturers such as Amkor. The absolute difference is only about 2%, indicating that the gap mainly comes from product definitions and rounding.
The chip counts are not exactly the same, however. Morgan Stanley expects about 5.92 million Rubin R200 units and about 1.04 million Rubin Ultra units, for a total of about 6.96 million units. J.P. Morgan uses different die-equivalent definitions for Rubin and Rubin Ultra. Packaging area, die count, and CoWoS-L layout differ, so chip units and wafer consumption do not map linearly. Similar wafer allocation is more valuable than similar per-chip forecasts.
Morgan Stanley’s explanation of Blackwell inventory also supports this production schedule. Chips, HBM, boards, networking, and rack-level deliveries naturally have timing gaps. Chips arriving first do not automatically mean end demand is weakening. Supply-chain buffers only turn into bad inventory if cloud capex, NVL72 rack volumes, and networking orders all weaken at the same time.
The investment implications for the NVIDIA chain are direct. CoWoS-L, HBM4, ABF substrates, and rack-scale systems still have high certainty, while TSMC continues to control the most difficult large-area packaging. Amkor will handle Vera CPUs and part of CoWoS-R; its upside depends on qualification and yield. Its certainty is lower than TSMC’s, but profit growth may be faster.
We now include HGX (8-GPU per server) in our chip consumption model and treat 9 HGX servers as equivalent to one NVL72 rack. We expect 5.4mn Blackwell units in 2026, and chip volume could meet Grace Blackwell NVL72 demand by 2H26. Our latest checks also suggest close to 7mn Rubin and Rubin Ultra units in 2027, while total Rubin NVL72 server racks could reach 90k in 2027 (Exhibit 12).
IV. AMD’s Comparable Gap Is 185k Wafers, About Two-Thirds Explained by Venice
AMD is the customer where the two models diverge the most. After unifying the Xilinx classification, J.P. Morgan is at 355k wafers and Morgan Stanley is at 540k wafers. The “240k wafers” in Morgan Stanley’s main text covers only the GPU portfolio and cannot be treated as AMD’s total advanced-packaging demand.
Venice explains most of the gap. Using Morgan Stanley’s per-wafer output assumption, the two CPU paths differ by about 120k-130k wafers, explaining about 67% of the comparable total gap. The remainder comes from the GPU mix and Morgan Stanley’s still-unexplained table definition gap.
This judgment moves CPUs from supporting components to incremental packaging drivers. Vera and Venice both require higher bandwidth, more complex interconnect, and more chiplet coordination, pushing traditional server CPU packaging closer to 2.5D. TSMC is prioritizing large-area accelerators such as Rubin, Feynman, and the MI series, while ASE Technology Holding and Amkor take on CPUs. OSATs therefore have a greater opportunity than their GPU share would imply.
Morgan Stanley’s high case still carries clear risks. AMD previously trimmed CoWoS bookings in 2026; Venice is AMD’s first server CPU to use CoWoS; and MI455/MI450 still need to prove real pull-in demand from Microsoft, AWS, Oracle, and Meta. If Venice falls below 5 million units, AMD cuts orders again, or OSAT yield remains stuck at the pilot-production stage, the 540k wafers of related demand could move back toward J.P. Morgan’s level.
V. ASIC Direction Is Consistent, but AWS and Packaging Routes Still Diverge
The two firms are broadly aligned on Google TPU and Broadcom. The allocation gap between Broadcom and MediaTek is within 20%, and TPU v8i Sunfish and v8t Zebrafish remain the largest custom-chip projects in 2027. The divergence mainly comes from chip counts, package area, and the classification of other networking projects; the exact figures have been aligned in the comparison table above.
The AWS gap is more worth tracking. Morgan Stanley lists AWS/Annapurna and AWS/Alchip at 90k and 36k wafers, respectively, while JPMorgan assigns 175k wafers to Alchip + AWS and allows some Trainium 3 spillover to Marvell Technology. JPMorgan expects roughly 3.5 million Trainium 3 units in 2027, versus Morgan Stanley’s roughly 2.38 million. If AWS ramps along JPMorgan’s path, Alchip, Marvell Technology, HBM, and OSAT would all gain additional slope.
Google TPU also provides a real test of an alternative route. JPMorgan expects the MediaTek-designed TPU v9 Humufish to use Intel EMIB-T, at roughly 50% of the cost of CoWoS-L, while supporting a larger package. Its substrate-level yield is about 60%, and substrate build-up and silicon-bridge embedding are still in the ramp phase. If TPU v10 adds SoIC logic stacking, MediaTek may move back to TSMC CoWoS-L to simplify manufacturing.
EMIB-T can support specific TPU, CPU, and a small number of Trainium projects, but in the near term it is unlikely to cover simultaneous high-end demand expansion from Nvidia, AMD, and multiple cloud vendors. From an investment perspective, Intel advanced packaging can be viewed as a pressure-release valve, while TSMC CoWoS-L remains the backbone. TPU v9 yield, the TPU v10 route, and the number of follow-on customers will determine whether that pressure-release valve can expand into a second main route.
VI. SoIC Moves to 2028, CoPoS Volume Production Lands in 2029
For advanced packaging roadmaps, the timeline matters more than the concept. JPMorgan expects TSMC SoIC year-end capacity to reach roughly 36kwpm in 2027 and rise to 65kwpm in 2028. Customers include AMD MI series, Apple M5 Max/Ultra, AWS Trainium 4, OpenAI Nexus 2, Meta MTIA 450/500, and some Feynman versions. The real large-scale demand comes from logic stacking, not today’s smaller-area optical-electrical chips.
AP7 phase 2 allocates more space to CoWoS, meaning the 2.5D shortage is addressed first in 2027, while large-scale SoIC volume ramp shifts later. This choice improves near-term delivery, but also raises the required 2028 ramp slope for 3D stacking equipment, hybrid bonding, testing, and yield. Equipment companies must wait for orders, acceptance, and utilization to appear; profits cannot be fully booked two years in advance based only on a roadmap.
CoPoS comes even later. JPMorgan believes engineering issues are still converging, with risk production beginning in early 2028 and volume production only possible in 2029. The interval between 2H28 Feynman and risk production is too short, so the first adopter is more likely to be a later Feynman Ultra. Including CoPoS in 2028 base supply would overstate that year’s effective capacity.
Near-term SoIC wafer consumption from optical interconnect also should not be exaggerated. JPMorgan believes EIC/PIC die areas are small, and 10–15kwpm can accommodate the current ramp. CPO will still affect switch chips, silicon photonics, FAU, and testing, but its packaging-capacity weight in 2027 is smaller than GPU, CPU, and TPU.
TPUs are likely to adopt SoIC only for v10. While the market is excited about CPO demand for SoIC (for EIC/PIC integration), the actual wafer demand is still quite small, in our view, given small die sizes. 10-15k wfpm can be accommodated with the current pace of capacity ramp.
Morgan Stanley CPO Glass-Bridge Deep-Dive Update: GlassBridge Replacement Anxiety, TSMC 25kwpm PIC, and FAU Supply-Chain Repricing
VII. Profit Ranking: TSMC Gets Certainty, OSAT Gets Verification Upside
TSMC receives the clearest cross-validation. Its 190–200kwpm internal capacity, roughly 1.2 million Nvidia wafers, and the retention of high-end CoWoS-L internally together support advanced-packaging revenue and pricing resilience. In Bank of America’s 2027 industry model, TSMC accounts for about 65% of global supply; in UBS’s model, about 71%. Although the statistical scopes differ, the conclusion that TSMC retains most high-difficulty capacity is unchanged.
OSAT receives the greatest upside, but also carries the greatest model risk. Morgan Stanley’s 80kwpm includes UMC, so it cannot be directly subtracted from JPMorgan’s 50kwpm OSAT scope. Bank of America puts ASE Technology Holding and Amkor together at 95–105kwpm, clearly higher than UBS’s 60kwpm. Realizable profit depends on how much of that capacity ultimately becomes qualified delivery from packaging houses. Verification conditions include Vera/Venice scheduling, customer certification, substrate supply, and mass-production yield. ASE Technology Holding has a broader customer base and technology reserve, Amkor is more sensitive to Nvidia CPU spillover, and Powertech Technology is closer to project-type opportunities.
JPMorgan sets TSMC’s target price at NT$3,100, using about 20x 12-month forward P/E. Morgan Stanley’s primary reference does not provide a target price on the same basis, so NT$3,100 can only be treated as JPMorgan’s scenario and should not be used for cross-institution high-low comparison. Multiple capacity estimates improve confidence in the business judgment, but they do not form a directly comparable target-price consensus.
Vanguard International Semiconductor’s position is also more specific. JPMorgan believes TSMC is selectively outsourcing interposer wafer manufacturing, so VIS benefits from front-end interposer capacity without directly bearing the full back-end complexity of CoWoS. If the outsourcing scope expands, VIS will gain incremental utilization; if TSMC only releases a small number of standardized steps, the profit contribution will be lower than the market imagines.
VIII. Three Scenarios and Verification Over the Next Four Quarters
The two reports can directly form scenario boundaries. JPMorgan represents tighter effective supply and a more conservative AMD view, while Morgan Stanley represents faster OSAT spillover and higher Venice. The middle scenario is used only for risk management, not as a third institution forecast.
Bank of America’s combined 95–105kwpm for ASE Technology Holding and Amkor can be used as a more aggressive external-supply stress test, but it is not suitable as a directly added fourth base scenario. This upper bound requires two OSATs to simultaneously complete the full CPU packaging ramp; if customer certification, substrate supply, or mass-production yield lags in even one area, nominal equipment cannot convert into effective output at the same scale.
Over the next four quarters, watch CPU first. Vera at 5.0 million–5.75 million units and Venice at 3.2 million–6.0 million units will determine CoWoS-R/L-like spillover. Whether AMD MI455 and MI450 combined can approach 1.5 million units, and whether AMD adjusts bookings again, will determine the credibility of the high scenario.
Second, watch OSAT effective output. Advanced-packaging revenue, capex, equipment arrival, customer certification, and yield disclosed by ASE Technology Holding and Amkor are more useful than “planned kwpm.” If JPMorgan’s 50kwpm can be delivered steadily, valuation can move closer to AI infrastructure rather than the traditional assembly-and-test cycle. If the incremental capacity in Morgan Stanley’s 80kwpm mainly comes from UMC or remains on the equipment nameplate, OSAT profit will still fall short of the broad-spillover scenario.
Third, watch the ASIC route. Quarterly shipments of Sunfish, Zebrafish, and Trainium 3, TPU v9 EMIB-T yield, and whether TPU v10 returns to CoWoS-L will determine the relative slopes for Broadcom, MediaTek, Alchip, Marvell Technology, and Intel. A one-quarter project delay only changes revenue timing; cancellation or supplier switching changes long-term value.
Finally, watch SoIC and CoPoS. SoIC at roughly 36kwpm by end-2027, 65kwpm by end-2028, CoPoS risk production in 2028, and volume production in 2029 are three clear time anchors. Any earlier equipment orders and customer certification would revise long-term value upward; if risk production continues to move out, valuations for related equipment and materials should come down.
IX. Conclusion: The Firmest Consensus Is at TSMC; the Largest Return Dispersion Is in OSAT
The eight institutions together draw a more complete boundary for CoWoS in 2027. TSMC’s latest direct estimate of 190-200 kwpm and Nvidia’s roughly 1.2 million wafers sit in the high-conviction zone. Global supply of 210-280 kwpm, external nominal capacity of 50-105 kwpm, and AMD-related demand of 355,000-540,000 wafers need to be verified separately by statistical scope and timing. Research should price the consensus base and the optionality separately.
TSMC continues to capture the hardest CoWoS-L work and the certainty from major customers. Nvidia and HBM maintain the demand floor. ASE Technology Holding, Amkor, and Vanguard International Semiconductor have capacity-spillover opportunities, but whether revenue materializes depends on effective yield and customer qualification. AMD, AWS, TPU, and EMIB-T offer higher optionality, but are also more vulnerable to disruption from a single product delay, architecture switch, or customer order cut.
The four most important numbers ahead are: TSMC’s quarterly effective CoWoS output, qualified OSAT output, actual Venice chip volume, and changes in AMD bookings. If all four move upward at the same time, Morgan Stanley’s broad-spillover scenario moves closer to reality. If CPU demand is weak or OSAT yield falls short, J.P. Morgan’s tight-supply scenario will prevail. The kwpm numbers reported by each house are only the starting point. Whether profit remains at TSMC or spreads to the OSAT and ASIC chains will ultimately be decided by these four verifiable data points.
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目录
TL;DR
1. First Split the Eight Brokers Into Three Different Scopes; 190–200kwpm Is the Real Consensus
JPMorgan, Morgan Stanley, and Goldman Sachs Are All Revising Up
II. 240 kwpm Is Still Tight; the Shortage Is Embedded in Full-Year Effective Output
III. NVIDIA at About 1.2 Million Wafers; Supply-Chain Consensus Is Already Strong
IV. AMD’s Comparable Gap Is 185k Wafers, About Two-Thirds Explained by Venice
V. ASIC Direction Is Consistent, but AWS and Packaging Routes Still Diverge
VI. SoIC Moves to 2028, CoPoS Volume Production Lands in 2029
VII. Profit Ranking: TSMC Gets Certainty, OSAT Gets Verification Upside
VIII. Three Scenarios and Verification Over the Next Four Quarters
IX. Conclusion: The Firmest Consensus Is at TSMC; the Largest Return Dispersion Is in OSAT
本内容基于公开资料和研报数据整理，不构成任何投资建议，不代表任何个人观点，仅供学习参考，请理性阅读
After incorporating Goldman Sachs, UBS, BofA, Nomura, Citi, and HSBC, 190–200kwpm remains the latest single-company consensus for TSMC, while the global view is 210–280kwpm. The gap mainly reflects differences in dates, WMCM, CoW, and OSAT boundaries; profit spillover depends on whether 50–105kwpm of external nominal capacity can become qualified delivery.
TL;DR
190–200kwpm remains the latest direct consensus. UBS put TSMC at 150kwpm on May 21, BofA at 180kwpm on June 24, JPMorgan at 190kwpm on July 10, and Morgan Stanley at 200kwpm on July 8. These four figures carry different dates and should not be treated as four same-day forecasts; the two most recent direct estimates differ by only 5%.
The comparable range for global supply is 210–280kwpm. UBS, JPMorgan, BofA, and Morgan Stanley put 2027 year-end global or industry capacity at 210, 240, 275, and 280kwpm, respectively. Goldman Sachs also gives 280kwpm, but it includes WMCM; this indicates broader TSMC back-end space and should not be mixed into a pure CoWoS high-low ranking.
Sell-side forecasts are converging upward. JPMorgan raised its 2027 year-end TSMC capacity estimate from 155kwpm in April to 190kwpm in July, while Morgan Stanley raised its estimate from 165kwpm to 200kwpm in late May and has maintained it since. Goldman Sachs also raised its 2027 annual capacity including WMCM from 2,490k to 2,730k; the directional message is more consistent than the static high-low comparison.
The external capacity range has widened to 50–105kwpm. JPMorgan assigns 50kwpm to OSATs, UBS 60kwpm, Morgan Stanley 80kwpm but includes UMC, while BofA splits ASE Technology Holding and Amkor into 95–105kwpm. The wider range comes from statistical boundaries and report timing; ASE Technology Holding and Amkor’s yield and customer qualification will determine the extent of profit spillover.
AMD-related demand falls in the 355k–540k wafer range. After standardizing the Xilinx classification, Morgan Stanley remains clearly above JPMorgan, with Venice CPU the largest single source of difference. The key follow-ups are actual Venice shipments, MI455/MI450 customer pull-ins, and whether AMD cuts bookings again; these will determine whether the high-case scenario holds.
CPUs are reshaping the advanced-packaging division of labor. In 2027, Vera is about 5 million units and Venice about 3.2 million–6 million units, as server CPUs begin adopting 2.5D advanced packaging at scale. TSMC is prioritizing large-area CoWoS-L accelerators, with more CPUs handed to ASE Technology Holding and Amkor. Multiple brokers recognize this division of labor, with disagreements concentrated on CPU volume and OSAT yield.
SoIC and CoPoS will not release supply immediately. JPMorgan believes 50%–60% of AP7 Phase 2 resources have already been shifted to CoWoS, while SoIC year-end capacity does not rise to 65kwpm until 2028; CoPoS is expected to enter risk production in 2028 and mass production in 2029. Intel EMIB-T can absorb some TPU projects, but with around 60% substrate-level yield and uncertainty over subsequent customers, it can only provide partial relief for now.
1. First Split the Eight Brokers Into Three Different Scopes; 190–200kwpm Is the Real Consensus
After recent broker reports are put on the same basis, the capacity divergence has a clear hierarchy. The first layer is TSMC standalone, where the two most recent direct estimates land at 190–200kwpm; the second layer is TSMC plus external supply, which reaches 210–280kwpm by end-2027; the third layer is customer allocation, where HSBC assigns 480k wafers to Broadcom. Such numbers explain demand, but cannot be included in total capacity rankings.
The annual basis also needs to be separated. Nomura lists full CoWoS output and CoW front-end targets separately, while Citi’s historical benchmark and JPMorgan’s latest report both point to about 2,000k for the full year. Effective output on a narrow basis is roughly 1.85 million–2.00 million. Goldman Sachs’ 2,730k includes WMCM, reflecting broader back-end capability, and cannot be used to prove that pure CoWoS is 40% higher than other brokers’ estimates.
This table should not be ranked mechanically by number. The newer the report, the stronger the CPU and ASIC pull-ins visible to the broker; the broader the range, the easier it is to include WMCM, CoW front-end, or external CoWoS-like 2.5D packaging. There are only two comparable conclusions: the latest TSMC standalone estimates have moved close to 190–200kwpm, and global supply still needs more than 50kwpm of external capability to meet demand.
JPMorgan, Morgan Stanley, and Goldman Sachs Are All Revising Up
Cross-sectional comparison answers “what each broker thinks now”; the timeline answers “where the supply chain is moving.” All three brokers have pushed up their 2027 forecasts, making 190–200kwpm look more like the new TSMC standalone anchor than a coincidence across two reports.
The eight brokers provide total-volume boundaries, while the two July reports further break down customers and quarters. Morgan Stanley listed 2027 customer allocations on July 8, 2026; JPMorgan added the quarterly capacity paths for TSMC, OSATs, SoIC, and CoPoS on July 10. Putting the two tables together lets us map certainty and optionality to specific customers.
Certainty comes from two numbers. TSMC’s 2027 year-end in-house CoWoS capacity is 190–200kwpm, and Nvidia’s annual consumption is 1,196k–1,222k wafers. The error bands on both are small, indicating strong supply-chain consensus around the largest fab and the largest customer.
The optionality is concentrated in three areas. Morgan Stanley’s year-end non-TSMC capacity is superficially 30kwpm higher than JPMorgan’s OSAT scope; after standardizing the Xilinx classification, Morgan Stanley’s AMD-related demand is 185k wafers above JPMorgan’s; the two brokers also classify AWS and some custom chips differently. These gaps directly determine the revenue slope for ASE Technology Holding, Amkor, Alchip, Marvell Technology, and related substrate and testing companies.
The scope boundaries must be stated first. Annual consumption is k wafers/year, while capacity is kwpm or kwfpm, representing nominal monthly capacity; year-end monthly capacity cannot simply be multiplied by 12 and treated as full-year effective supply. JPMorgan’s table also notes that customer allocations are not yield-adjusted, while Morgan Stanley’s high-level customer table and product-detail table have a 30k gap; total demand should therefore be presented as a range.
II. 240 kwpm Is Still Tight; the Shortage Is Embedded in Full-Year Effective Output
J.P. Morgan raised its estimate for TSMC’s CoWoS capacity at end-2027 to 190 kwpm and OSAT capacity to 50 kwpm, for a combined 240 kwpm. It also said the near-term supply-demand gap has widened to roughly 20%, an institutional estimate. Both statements can be true, because 240 kwpm only represents nominal capacity at the end of the fourth quarter.
J.P. Morgan’s quarterly path better explains the pressure. TSMC rises from 130 kwpm in 1Q27 to 157, 175, and 190 kwpm by quarter, while OSAT rises from 22 kwpm to 30, 40, and 50 kwpm. A simple annualized stress test using average quarter-end nominal capacity is about 2,382k wafers, which is not the same as actual full-year output. The customer allocation table implies full-year demand of 2,381k wafers, leaving almost no nominal surplus.
A normal manufacturing system needs buffers for maintenance, line changeovers, yield, substrate shortages, and new-product ramp. Rubin Ultra uses dual dies; high-end Feynman versions may reach 9-10x reticle size; MI500 is more likely to reach 14-15x. The packaging area and process time consumed by the same chip continue to rise, making nominal wafer counts an increasingly weak proxy for real delivery capacity.
Including other institutions, external nominal capacity expands from 50 kwpm to around 105 kwpm. J.P. Morgan assigns OSAT 50 kwpm; UBS assigns 60 kwpm; Morgan Stanley assigns 80 kwpm but includes UMC; Bank of America separates ASE Technology Holding and Amkor at 70-75 kwpm and 25-30 kwpm, respectively. These numbers reflect different statistical boundaries and expansion assumptions, and cannot be treated as a like-for-like ranking.
Morgan Stanley’s supply assumption is wider. It expects TSMC at 200 kwpm and non-TSMC at 80 kwpm by end-2027. Its chart combines Amkor, UMC, and ASE Technology Holding, but does not disclose a company-by-company breakdown. J.P. Morgan assigns OSAT CoWoS-like capacity of 50 kwpm. The 30 kwpm difference can only be viewed as a headline gap; the confirmable disagreement lies in the speed of external outsourcing and effective yield.
At the same time, OSAT capacity expansion for CoWoS-like processes is picking up momentum, and we expect OSATs CoWoS-like capacity to reach 15k/50k/85k wfpm by end 26/27/28. Bulk of OSAT capacity is likely to be deployed for server CPU packaging, followed by networking and small volumes for accelerator chips such as LPU or Trainium 3. Overall, the demand-supply gap has recently expanded to ~20%, given the meaningful upside from agentic AI CPU demand.
TSMC is reallocating back-end space. J.P. Morgan believes AP7 Phase 2 was originally planned entirely for SoIC, but about 50%-60% has now been shifted to CoWoS. Some interposer wafer manufacturing is being selectively outsourced to Vanguard International Semiconductor, and CoWoS-R is expanding again. TSMC is retaining large-area, high-complexity accelerators, while CPUs, networking chips, and small volumes of accelerators are moving more to OSATs. This is a clear division of profit pools.
III. NVIDIA at About 1.2 Million Wafers; Supply-Chain Consensus Is Already Strong
NVIDIA is the most stable anchor across the two reports. Both forecasts land at around 1.2 million wafers, with TSMC handling close to 90% and the remainder mainly shared by external manufacturers such as Amkor. The absolute difference is only about 2%, indicating that the gap mainly comes from product definitions and rounding.
The chip counts are not exactly the same, however. Morgan Stanley expects about 5.92 million Rubin R200 units and about 1.04 million Rubin Ultra units, for a total of about 6.96 million units. J.P. Morgan uses different die-equivalent definitions for Rubin and Rubin Ultra. Packaging area, die count, and CoWoS-L layout differ, so chip units and wafer consumption do not map linearly. Similar wafer allocation is more valuable than similar per-chip forecasts.
Morgan Stanley’s explanation of Blackwell inventory also supports this production schedule. Chips, HBM, boards, networking, and rack-level deliveries naturally have timing gaps. Chips arriving first do not automatically mean end demand is weakening. Supply-chain buffers only turn into bad inventory if cloud capex, NVL72 rack volumes, and networking orders all weaken at the same time.
The investment implications for the NVIDIA chain are direct. CoWoS-L, HBM4, ABF substrates, and rack-scale systems still have high certainty, while TSMC continues to control the most difficult large-area packaging. Amkor will handle Vera CPUs and part of CoWoS-R; its upside depends on qualification and yield. Its certainty is lower than TSMC’s, but profit growth may be faster.
We now include HGX (8-GPU per server) in our chip consumption model and treat 9 HGX servers as equivalent to one NVL72 rack. We expect 5.4mn Blackwell units in 2026, and chip volume could meet Grace Blackwell NVL72 demand by 2H26. Our latest checks also suggest close to 7mn Rubin and Rubin Ultra units in 2027, while total Rubin NVL72 server racks could reach 90k in 2027 (Exhibit 12).
IV. AMD’s Comparable Gap Is 185k Wafers, About Two-Thirds Explained by Venice
AMD is the customer where the two models diverge the most. After unifying the Xilinx classification, J.P. Morgan is at 355k wafers and Morgan Stanley is at 540k wafers. The “240k wafers” in Morgan Stanley’s main text covers only the GPU portfolio and cannot be treated as AMD’s total advanced-packaging demand.
Venice explains most of the gap. Using Morgan Stanley’s per-wafer output assumption, the two CPU paths differ by about 120k-130k wafers, explaining about 67% of the comparable total gap. The remainder comes from the GPU mix and Morgan Stanley’s still-unexplained table definition gap.
This judgment moves CPUs from supporting components to incremental packaging drivers. Vera and Venice both require higher bandwidth, more complex interconnect, and more chiplet coordination, pushing traditional server CPU packaging closer to 2.5D. TSMC is prioritizing large-area accelerators such as Rubin, Feynman, and the MI series, while ASE Technology Holding and Amkor take on CPUs. OSATs therefore have a greater opportunity than their GPU share would imply.
Morgan Stanley’s high case still carries clear risks. AMD previously trimmed CoWoS bookings in 2026; Venice is AMD’s first server CPU to use CoWoS; and MI455/MI450 still need to prove real pull-in demand from Microsoft, AWS, Oracle, and Meta. If Venice falls below 5 million units, AMD cuts orders again, or OSAT yield remains stuck at the pilot-production stage, the 540k wafers of related demand could move back toward J.P. Morgan’s level.
V. ASIC Direction Is Consistent, but AWS and Packaging Routes Still Diverge
The two firms are broadly aligned on Google TPU and Broadcom. The allocation gap between Broadcom and MediaTek is within 20%, and TPU v8i Sunfish and v8t Zebrafish remain the largest custom-chip projects in 2027. The divergence mainly comes from chip counts, package area, and the classification of other networking projects; the exact figures have been aligned in the comparison table above.
The AWS gap is more worth tracking. Morgan Stanley lists AWS/Annapurna and AWS/Alchip at 90k and 36k wafers, respectively, while JPMorgan assigns 175k wafers to Alchip + AWS and allows some Trainium 3 spillover to Marvell Technology. JPMorgan expects roughly 3.5 million Trainium 3 units in 2027, versus Morgan Stanley’s roughly 2.38 million. If AWS ramps along JPMorgan’s path, Alchip, Marvell Technology, HBM, and OSAT would all gain additional slope.
Google TPU also provides a real test of an alternative route. JPMorgan expects the MediaTek-designed TPU v9 Humufish to use Intel EMIB-T, at roughly 50% of the cost of CoWoS-L, while supporting a larger package. Its substrate-level yield is about 60%, and substrate build-up and silicon-bridge embedding are still in the ramp phase. If TPU v10 adds SoIC logic stacking, MediaTek may move back to TSMC CoWoS-L to simplify manufacturing.
EMIB-T can support specific TPU, CPU, and a small number of Trainium projects, but in the near term it is unlikely to cover simultaneous high-end demand expansion from Nvidia, AMD, and multiple cloud vendors. From an investment perspective, Intel advanced packaging can be viewed as a pressure-release valve, while TSMC CoWoS-L remains the backbone. TPU v9 yield, the TPU v10 route, and the number of follow-on customers will determine whether that pressure-release valve can expand into a second main route.
VI. SoIC Moves to 2028, CoPoS Volume Production Lands in 2029
For advanced packaging roadmaps, the timeline matters more than the concept. JPMorgan expects TSMC SoIC year-end capacity to reach roughly 36kwpm in 2027 and rise to 65kwpm in 2028. Customers include AMD MI series, Apple M5 Max/Ultra, AWS Trainium 4, OpenAI Nexus 2, Meta MTIA 450/500, and some Feynman versions. The real large-scale demand comes from logic stacking, not today’s smaller-area optical-electrical chips.
AP7 phase 2 allocates more space to CoWoS, meaning the 2.5D shortage is addressed first in 2027, while large-scale SoIC volume ramp shifts later. This choice improves near-term delivery, but also raises the required 2028 ramp slope for 3D stacking equipment, hybrid bonding, testing, and yield. Equipment companies must wait for orders, acceptance, and utilization to appear; profits cannot be fully booked two years in advance based only on a roadmap.
CoPoS comes even later. JPMorgan believes engineering issues are still converging, with risk production beginning in early 2028 and volume production only possible in 2029. The interval between 2H28 Feynman and risk production is too short, so the first adopter is more likely to be a later Feynman Ultra. Including CoPoS in 2028 base supply would overstate that year’s effective capacity.
Near-term SoIC wafer consumption from optical interconnect also should not be exaggerated. JPMorgan believes EIC/PIC die areas are small, and 10–15kwpm can accommodate the current ramp. CPO will still affect switch chips, silicon photonics, FAU, and testing, but its packaging-capacity weight in 2027 is smaller than GPU, CPU, and TPU.
TPUs are likely to adopt SoIC only for v10. While the market is excited about CPO demand for SoIC (for EIC/PIC integration), the actual wafer demand is still quite small, in our view, given small die sizes. 10-15k wfpm can be accommodated with the current pace of capacity ramp.
Morgan Stanley CPO Glass-Bridge Deep-Dive Update: GlassBridge Replacement Anxiety, TSMC 25kwpm PIC, and FAU Supply-Chain Repricing
VII. Profit Ranking: TSMC Gets Certainty, OSAT Gets Verification Upside
TSMC receives the clearest cross-validation. Its 190–200kwpm internal capacity, roughly 1.2 million Nvidia wafers, and the retention of high-end CoWoS-L internally together support advanced-packaging revenue and pricing resilience. In Bank of America’s 2027 industry model, TSMC accounts for about 65% of global supply; in UBS’s model, about 71%. Although the statistical scopes differ, the conclusion that TSMC retains most high-difficulty capacity is unchanged.
OSAT receives the greatest upside, but also carries the greatest model risk. Morgan Stanley’s 80kwpm includes UMC, so it cannot be directly subtracted from JPMorgan’s 50kwpm OSAT scope. Bank of America puts ASE Technology Holding and Amkor together at 95–105kwpm, clearly higher than UBS’s 60kwpm. Realizable profit depends on how much of that capacity ultimately becomes qualified delivery from packaging houses. Verification conditions include Vera/Venice scheduling, customer certification, substrate supply, and mass-production yield. ASE Technology Holding has a broader customer base and technology reserve, Amkor is more sensitive to Nvidia CPU spillover, and Powertech Technology is closer to project-type opportunities.
JPMorgan sets TSMC’s target price at NT$3,100, using about 20x 12-month forward P/E. Morgan Stanley’s primary reference does not provide a target price on the same basis, so NT$3,100 can only be treated as JPMorgan’s scenario and should not be used for cross-institution high-low comparison. Multiple capacity estimates improve confidence in the business judgment, but they do not form a directly comparable target-price consensus.
Vanguard International Semiconductor’s position is also more specific. JPMorgan believes TSMC is selectively outsourcing interposer wafer manufacturing, so VIS benefits from front-end interposer capacity without directly bearing the full back-end complexity of CoWoS. If the outsourcing scope expands, VIS will gain incremental utilization; if TSMC only releases a small number of standardized steps, the profit contribution will be lower than the market imagines.
VIII. Three Scenarios and Verification Over the Next Four Quarters
The two reports can directly form scenario boundaries. JPMorgan represents tighter effective supply and a more conservative AMD view, while Morgan Stanley represents faster OSAT spillover and higher Venice. The middle scenario is used only for risk management, not as a third institution forecast.
Bank of America’s combined 95–105kwpm for ASE Technology Holding and Amkor can be used as a more aggressive external-supply stress test, but it is not suitable as a directly added fourth base scenario. This upper bound requires two OSATs to simultaneously complete the full CPU packaging ramp; if customer certification, substrate supply, or mass-production yield lags in even one area, nominal equipment cannot convert into effective output at the same scale.
Over the next four quarters, watch CPU first. Vera at 5.0 million–5.75 million units and Venice at 3.2 million–6.0 million units will determine CoWoS-R/L-like spillover. Whether AMD MI455 and MI450 combined can approach 1.5 million units, and whether AMD adjusts bookings again, will determine the credibility of the high scenario.
Second, watch OSAT effective output. Advanced-packaging revenue, capex, equipment arrival, customer certification, and yield disclosed by ASE Technology Holding and Amkor are more useful than “planned kwpm.” If JPMorgan’s 50kwpm can be delivered steadily, valuation can move closer to AI infrastructure rather than the traditional assembly-and-test cycle. If the incremental capacity in Morgan Stanley’s 80kwpm mainly comes from UMC or remains on the equipment nameplate, OSAT profit will still fall short of the broad-spillover scenario.
Third, watch the ASIC route. Quarterly shipments of Sunfish, Zebrafish, and Trainium 3, TPU v9 EMIB-T yield, and whether TPU v10 returns to CoWoS-L will determine the relative slopes for Broadcom, MediaTek, Alchip, Marvell Technology, and Intel. A one-quarter project delay only changes revenue timing; cancellation or supplier switching changes long-term value.
Finally, watch SoIC and CoPoS. SoIC at roughly 36kwpm by end-2027, 65kwpm by end-2028, CoPoS risk production in 2028, and volume production in 2029 are three clear time anchors. Any earlier equipment orders and customer certification would revise long-term value upward; if risk production continues to move out, valuations for related equipment and materials should come down.
IX. Conclusion: The Firmest Consensus Is at TSMC; the Largest Return Dispersion Is in OSAT
The eight institutions together draw a more complete boundary for CoWoS in 2027. TSMC’s latest direct estimate of 190-200 kwpm and Nvidia’s roughly 1.2 million wafers sit in the high-conviction zone. Global supply of 210-280 kwpm, external nominal capacity of 50-105 kwpm, and AMD-related demand of 355,000-540,000 wafers need to be verified separately by statistical scope and timing. Research should price the consensus base and the optionality separately.
TSMC continues to capture the hardest CoWoS-L work and the certainty from major customers. Nvidia and HBM maintain the demand floor. ASE Technology Holding, Amkor, and Vanguard International Semiconductor have capacity-spillover opportunities, but whether revenue materializes depends on effective yield and customer qualification. AMD, AWS, TPU, and EMIB-T offer higher optionality, but are also more vulnerable to disruption from a single product delay, architecture switch, or customer order cut.
The four most important numbers ahead are: TSMC’s quarterly effective CoWoS output, qualified OSAT output, actual Venice chip volume, and changes in AMD bookings. If all four move upward at the same time, Morgan Stanley’s broad-spillover scenario moves closer to reality. If CPU demand is weak or OSAT yield falls short, J.P. Morgan’s tight-supply scenario will prevail. The kwpm numbers reported by each house are only the starting point. Whether profit remains at TSMC or spreads to the OSAT and ASIC chains will ultimately be decided by these four verifiable data points.