Intel vs. TSMC in Advanced Packaging: Can EMIB-T’s Cost and Size Advantages Break Through CoPoS’s Performance Moat?
目录
Executive Summary
1. Advanced Packaging Is Competing for a Second Platform Slot
2. Bridges vs. Interposers: One Less Layer, but the Complexity Has Simply Moved
3. Why the Cost Advantage Could Be Real—and Why Yield Can So Easily Reverse It
4. Size Is EMIB-T’s Clearest Opening, but the Window Will Not Remain Open Forever
5. Two Tests in 2028: Google TPU v9 and Nvidia Feynman
6. Supply-Chain Gains Will Not Be Broad-Based: Value Will Flow to Substrates, Bonding, and Yield Control
7. The Glass Theme Is the Easiest to Trade Prematurely—and the Most Important to Split into Two Distinct Issues
8. How to Determine Who Is Winning: Three Mass-Production Gates Matter More Than Market-Share Slogans
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AI packaging is shifting from a single dominant platform toward limited diversification, with cost, size, performance, and yield jointly determining the respective boundaries of Intel and TSMC.
Executive Summary
EMIB-T is first and foremost a second source, not a replacement for TSMC. UBS expects the advanced-packaging market to grow from US$19 billion in 2026 to US$122 billion in 2030, representing a 59% CAGR. As the market expands by more than 6-fold, Intel could capture a 13%–18% share while TSMC retains 62%–67%, allowing both companies to grow simultaneously.
The two architectures address the same bottleneck but optimize for different objectives. EMIB-T eliminates the silicon interposer spanning the entire package, instead connecting compute dies and high-bandwidth memory (HBM) through localized silicon bridges embedded in an ABF organic substrate. This shortens the process flow, theoretically lowers costs, and makes scaling beyond 14× reticle size easier. CoPoS moves the redistribution-layer (RDL) interposer from a circular wafer to a square panel, offering higher interconnect density, stronger signal and power integrity, greater 3D-stacking capability, and better support for future co-packaged optics.
Intel’s central challenge is whether a “lower-cost structure” can translate into a “lower-cost finished package.” UBS says EMIB-T package yield during validation is approximately 90%–92%, but high-value compute dies and HBM require mass-production yields near the high-90% range. Substrate yield is estimated at approximately 50%, materially below the more than 80% achieved by high-performance-computing ABF substrates. If yields are insufficient, scrap losses will consume the interposer-related savings.
TSMC’s central challenge is whether panel processing can replicate the stability of wafer processing. First-generation CoPoS is scheduled to use 310 × 310 mm² panels and enter mass production in 2028, followed by expansion to 510 × 515 mm². Warpage, panel uniformity, the qualification of new equipment, and yield ramp-up will determine whether its performance advantages can be realized on schedule.
2028 is the convergence point for customer validation. UBS believes EMIB-T’s first major external project could be Google TPU v9, developed with MediaTek’s participation; CoPoS’s first major customer could be Nvidia Feynman, followed by expansion to AMD and custom AI chips (ASICs). Substrate capacity, thermocompression-bonding equipment orders, customer-product tape-outs, and mass-production yields are the real leading indicators.
Supply-chain value will shift from “everyone benefits” toward “whoever resolves the bottleneck.” EMIB-T transfers more complexity to the substrate, making Ibiden and potential second source Unimicron the most direct beneficiaries. CoPoS increases demand for panel wet processing, placement, underfill, and metrology. Glass carriers are only process supports, while glass-core substrates are a variable for 2029–2030 or later; they should not be combined into a single near-term investment theme.
1. Advanced Packaging Is Competing for a Second Platform Slot
Over the past two years, advanced packaging has often been misread as a capacity race: whoever builds another production line captures another share of revenue. In reality, it is closer to a competition in system delivery. The compute dies, HBM, interconnects, power delivery, and thermal management of AI accelerators jointly determine whether finished products can be delivered on schedule. A packaging platform must simultaneously manage front-end wafers, known-good dies, substrates, bonding, testing, and responsibility for yields.
In our previous report, “TSMC CoWoS Deep Dive: 200 kwpm Packaging, US$75 Billion CapEx, and the Reallocation Across CPUs, GPUs, ASICs, and Optical Interconnects”, our baseline view was that capacity expansion by outsourced semiconductor assembly and test providers and substrate manufacturers could broaden the ecosystem, but did not mean TSMC would lose its leadership. Customers are purchasing not merely a packaging step, but predictable system delivery.
UBS’s report does not overturn that view; instead, it quantifies the “second-source” opportunity. Its stress scenario assumes Intel captures a 13% share by 2030, generating approximately US$16 billion in advanced-packaging revenue. This would correspond roughly to 24 million AI-accelerator dies, or 6 million chipsets containing 4 compute dies each. Even in this scenario, TSMC could retain 65%–70% of the market, with advanced-packaging revenue growing at approximately a 50% CAGR from 2026 to 2030. A more favorable scenario for Intel raises its share to 18%, while TSMC still retains 62%.
These figures do not imply that the forecast will necessarily materialize. Rather, they define a boundary: once the market expands from US$19 billion to US$122 billion, declining market share and rising revenue can occur simultaneously. Intel’s success would first mean that advanced packaging is shifting from a single platform to “a primary platform plus a credible second source.” TSMC could lose part of the incremental market without necessarily losing pricing power or its position at the technological center.
2. Bridges vs. Interposers: One Less Layer, but the Complexity Has Simply Moved
EMIB-T and CoPoS address the same problem: as individual dies approach the reticle limit, system performance increasingly depends on multiple dies and more HBM, driving increases in package area, interconnect distance, and power-delivery difficulty. The difference between the two can be understood as “building localized bridges” versus “laying an entire high-speed road network.”
EMIB-T embeds small silicon bridges in a large organic substrate, using silicon only where high-speed connections are required between compute dies and HBM. Through-silicon vias within the bridges provide vertical power delivery for HBM4 and subsequent products, while the compute dies and HBM are placed directly on the substrate. Because no silicon interposer spans the entire package, the process flow is shorter, and the square substrate avoids the substantial edge waste associated with circular wafers. The larger the package, the more pronounced this area-utilization advantage becomes.
CoPoS continues TSMC’s approach of using an RDL interposer to organize high-speed interconnects, but changes the production carrier from a circular wafer to a square or rectangular panel. Its objective is not merely to make CoWoS “larger,” but also to increase interconnect density, shorten signal paths, improve power integrity, and accommodate embedded capacitors, SoIC 3D stacking, and future co-packaged optics. The trade-off is a larger number of process layers and higher requirements for panel uniformity, warpage control, and equipment coordination.
EMIB-T Is More Focused on Scale and Cost, While CoPoS Is More Focused on Performance and Integration
Therefore, “EMIB-T eliminates the interposer” does not mean that complexity disappears. Silicon-bridge embedding, alignment, upper and lower metal contacts, and thermal-stress control are all transferred to substrate manufacturing. Nor is CoPoS simply a matter of cutting a circular wafer into a square shape; panel-level processing must achieve the stability required for high-value AI packaging. The relative merits of the architectures must ultimately be translated into yield and delivery-cycle performance.
3. Why the Cost Advantage Could Be Real—and Why Yield Can So Easily Reverse It
The theoretical cost logic for EMIB-T is straightforward: eliminate the large-area silicon interposer, reduce certain process steps, and use a square substrate to improve material utilization for ultra-large packages. Bernstein’s February 2026 report had already suggested that, excluding yield considerations, EMIB-T’s total packaging cost could be lower than that of the corresponding CoWoS generation. UBS’s July update advances the question from “Is the structure cheaper?” to “Can mass-production yield preserve the cost advantage?”
UBS’s industry research indicates that EMIB-T package yield during validation is approximately 90%–92%, but this result cannot be directly extrapolated to large-scale production. Once compute dies and multiple HBM stacks are incorporated, a single packaging failure can scrap several high-value components simultaneously, and customers generally require stable yields near the high-90% range. The substrate is even more challenging: UBS estimates EMIB-T substrate yield at approximately 50%, compared with approximately 60% for conventional EMIB substrates and more than 80% for mature high-performance-computing ABF substrates.
This produces a counterintuitive result. EMIB-T removes interposer value from TSMC’s side of the supply chain, but adds the difficulty of silicon bridges, upper and lower contacts, and precision alignment to the substrate side. Substrate prices and scrap costs consequently rise. Whenever final yield falls below a critical threshold, the interposer and process-flow savings achieved by customers could be offset by defective substrates, failed packages, delivery delays, and losses on expensive dies.
TSMC’s cost pressure comes from the opposite direction. Once package size exceeds 10× reticle size, the number of usable large packages that can be arranged on a circular wafer declines rapidly, while edge waste and warpage in CoWoS become more pronounced. CoPoS adopts panels precisely to restore area utilization and expand output. TSMC must demonstrate that the cost of new panel equipment, additional process controls, and complex integration can be covered by higher performance, higher yield, and the value of shorter customer time to market.
Cost comparisons therefore cannot stop at the bill of materials. A more useful metric is “total cost per good package,” which should include at least substrate yield, bonding yield, known-good-die losses, equipment depreciation, rework, testing, and ramp-up time. If Intel discloses only structural costs without stable yields, the cost advantage remains an option. If TSMC demonstrates only panel size without mass-production uniformity, its performance advantage has not yet translated into revenue either.
4. Size Is EMIB-T’s Clearest Opening, but the Window Will Not Remain Open Forever
AI packaging is shifting from “putting in more transistors” toward “putting in more compute dies and HBM.” UBS believes EMIB-T’s approach of building chipsets directly on large substrates makes it easier to support packages of 14× reticle size or larger. For hyperscalers, this offers a practical choice: if the objective is to increase the number of compute dies and HBM stacks quickly, rather than pursue the densest possible 3D integration, EMIB-T may be more attractive.
This advantage, however, is time-limited. TSMC plans to launch CoPoS with 310 × 310 mm² panels and migrate to 510 × 515 mm² once the process matures. It has also proposed expanding CoWoS to 14× reticle size by 2028, accommodating 10 large compute dies and 20 HBM stacks. In other words, EMIB-T’s current size leadership resembles a first-mover window rather than a permanent barrier. Once large-panel CoPoS completes its yield ramp, the gap will narrow.
Customers will compare not only maximum size but also migration costs. TSMC can place leading-edge processes, CoWoS, SoIC, testing, and future co-packaged optics on a single roadmap, creating a more centralized boundary of responsibility. If an external EMIB-T customer continues to have its front-end wafers manufactured by TSMC and then transfers them to Intel for back-end packaging, the parties must redefine responsibility for transportation, known-good dies, fault attribution, and yield losses. Technical interfaces can be standardized, but commercial responsibility must be negotiated item by item.
This is also the moat that is hardest for TSMC’s competitors to replicate and most important for Intel to close. TSMC sells “integrated front-end and back-end certainty,” while Intel sells “larger packages, lower structural costs, and supply redundancy.” CoPoS has the advantage when customers prioritize time to market and maximum performance; EMIB-T’s probability of winning rises when customers already have mature chip designs and place greater emphasis on ultra-large package size and a second source.
5. Two Tests in 2028: Google TPU v9 and Nvidia Feynman
The mass-production roadmaps compress the competition between the two technologies into similar time windows. UBS expects EMIB-T to enter mass production from the second half of 2027 through 2028. Its first major external project could be Google TPU v9, developed with MediaTek’s participation, with the principal volume ramp in 2028. CoPoS is scheduled to enter mass production in 2028, with Nvidia Feynman potentially becoming its first major customer during the second half of 2028 through 2029, followed only thereafter by AMD and other custom ASICs.
Compared with the February materials, UBS’s July report provides more verifiable details: EMIB-T has achieved validation-stage package yield of 90%–92%, while estimated substrate yield is approximately 50%; Ibiden has formally announced a ¥220 billion investment in its Gama plant, targeting mass production by the end of 2027 and a ramp-up in 2028. The evidence has clearly advanced, but it has not crossed the final threshold—whether Google TPU v9 adopts the platform on schedule, whether mass-production yields meet targets, and whether Intel can deliver consistently.
Likewise, Nvidia Feynman is only a potential launch customer identified by UBS based on industry research, not confirmed mass-production revenue. If both programs proceed on schedule, the market will develop a clear segmentation: TSMC will serve flagship platforms seeking the highest performance and complete integration, while Intel will address part of the ultra-large custom-ASIC and second-source demand. If either party is delayed, customers will prioritize incumbent platforms with stable capacity rather than bear an unlimited waiting cost for a roadmap.
6. Supply-Chain Gains Will Not Be Broad-Based: Value Will Flow to Substrates, Bonding, and Yield Control
High-end ABF substrates are the most direct beneficiary of EMIB-T. Silicon bridges, through-silicon vias within the bridges, upper and lower metal contacts, and precision alignment all become part of substrate manufacturing, transforming the substrate from an ordinary carrier into an integrated platform that performs some interconnect and power-delivery functions. UBS identifies Ibiden as the primary supplier. It holds an approximately 70%–80% share of high-end ABF substrates for Nvidia Blackwell and Blackwell Ultra, giving it both a mass-production track record and experience in warpage control. If the incremental investment in the Gama plant is largely absorbed by the Google project, subsequent increases in capital expenditure will be an important indicator of demand strength.
Unimicron participated in earlier generations of EMIB and is also developing EMIB-T, but UBS says its current yields have yet to reach satisfactory levels. It is better viewed as a second-source option if volume exceeds expectations than as a preferred supplier with the same degree of certainty as Ibiden. Through its 2025 partnership with Intel, Amkor offers potential EMIB assembly capabilities in South Korea, Portugal, and the United States. In the near term, Intel is more likely to vertically integrate key external products within its own facilities while transferring certain steps for mature internal products to partners.
The incremental opportunities from CoPoS are more dispersed. Large panels could require greater use of thermocompression bonding during both chip placement and substrate assembly, making ASMPT and K&S; important suppliers. Wet processing, underfill, metrology, and panel carriers will also generate additional equipment demand. ASE Holdings could undertake part of the substrate assembly, while Amkor could participate in U.S.-based collaboration. The key is not to compile a list in which “every supplier benefits,” but to determine which companies can improve yield, shorten cycle times, or control warpage.
7. The Glass Theme Is the Easiest to Trade Prematurely—and the Most Important to Split into Two Distinct Issues
CoPoS involves glass, but “using glass” does not mean that glass-core substrates have entered mass production. In first-generation panel processing, glass primarily serves as a temporary carrier: compute dies and HBM are placed, molded, flipped, and debonded on the glass, after which the glass is removed from the finished product. Its value lies in flatness, stability, and suitability for large-panel processing, not in remaining permanently inside the package.
Glass-core substrates, by contrast, replace the conventional organic core layer with glass. Their greater rigidity theoretically makes them more suitable for packages exceeding 14× reticle size, but they require high-aspect-ratio through-glass vias, laser or etching processes, and copper filling, while also needing to resolve brittleness, microcracking, and reliability issues. The Ibiden roadmap cited by UBS places this milestone after 2030, while the report’s overall industry assessment is 2029–2030 or later.
The initial CoPoS and EMIB-T volume ramps in 2028 therefore do not depend on glass-core substrates. Combining demand for temporary carriers, glass-processing equipment, and the long-term value of glass cores into a single near-term revenue opportunity is a classic timing mismatch. In the near term, investors should track panel-carrier size, equipment validation, and yield; only over the longer term should the focus shift to through-glass vias, crack control, reliability certification, and adoption by customer platforms.
8. How to Determine Who Is Winning: Three Mass-Production Gates Matter More Than Market-Share Slogans
The first gate is yield. For EMIB-T, investors need to see substrate yield rise consistently from approximately 50%, package yield move from 90%–92% into the high-90% range, and these improvements occur under actual customer specifications rather than on simplified validation vehicles. CoPoS must demonstrate stable control of warpage, overlay, and uniformity on 310 × 310 mm² panels. Peak data without disclosure of lot-to-lot stability is insufficient to confirm mass production for either platform.
The second gate is a closed loop between customers and accountability. Google TPU v9 and Nvidia Feynman must progress from supply-chain speculation to confirmed capacity, product, and shipment milestones. Intel, in particular, must demonstrate that known-good dies can be tracked between TSMC’s front-end wafer manufacturing and Intel’s back-end packaging, defects can be located quickly, and responsibility for losses is assigned to a clearly identified party. Without this closed loop, a second source increases both supply options and management costs.
The third gate is capital efficiency. Additional investment by Ibiden, repeat purchases of thermocompression-bonding equipment, and TSMC’s qualification of first-generation CoPoS equipment vendors are all leading indicators of demand. Only capacity utilization, good-package output, and customer revenue, however, can demonstrate returns on investment. If Intel gains share primarily through low pricing and redundancy purchases, profit elasticity could be lower than revenue elasticity. If TSMC deploys substantial panel capital to defend market share but suffers a delayed ramp, depreciation will also erode its premium for high performance.
The most likely eventual outcome is neither EMIB-T defeating CoPoS nor CoPoS eliminating every alternative architecture, but rather performance-based segmentation in advanced packaging. TSMC will remain at the center of maximum performance, 3D integration, and complete system delivery, while Intel captures a share of custom AI chips through ultra-large package size, a shorter process flow, and second-source demand. UBS’s scenario of a 13%–18% share for Intel provides a reasonable upper-bound range for this coexistence.
The point at which valuations genuinely change will not be the next roadmap announcement. It will be when the same body of evidence emerges over several consecutive quarters in 2027–2028: customer products enter mass production on schedule, yields rise consistently, equipment orders repeat, substrate capacity is absorbed by genuine orders, and packaging revenue begins to cover incremental depreciation. Only then will EMIB-T evolve from “a technology option for Intel” into the second platform in advanced packaging; only then will CoPoS evolve from “an ambitious upgrade to CoWoS” into TSMC’s next source of sustainable cash flow.