目录
TL;DR
From “Does HBF Exist?” to “What Does HBF Look Like?”
HBF Addresses the High Cost of Data Movement, Not Insufficient Compute
UCIe Turns a Storage Issue into a System-Platform Issue
Why SK hynix Is Betting Simultaneously on HBM, HBF, and Enterprise SSDs
Impact on the Supply Chain: Incremental Value Will Extend Beyond NAND Manufacturers
Commercialization Still Faces Five Hurdles
How HBF, HBM, CXL Memory, and SSDs Will Divide Their Roles
Unit Economics Will Determine Whether HBF Is a Good Business
From Standard to Revenue: At Least Four Stages
What to Track Next
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SK hynix and Sandisk have released the first HBF standard specifications, moving high-bandwidth flash from concept demonstrations into the engineering phase of joint adoption across processors, packaging, and software, as the memory hierarchy for AI inference begins to be restructured.
TL;DR
The initial HBF specifications released by SK hynix and Sandisk cover capacities of up to 512GB, three bandwidth tiers ranging from 0.4TB/s to 3.0TB/s, and 8-layer and 16-layer NAND die stacks. HBF is therefore no longer merely a “faster NAND” concept, but a standardized product category with defined capacity, performance, and packaging boundaries.
HBF is positioned neither as a replacement for HBM nor as an enterprise SSD simply moved into the package. It sits between HBM and SSD: NAND handles large volumes of relatively cold data, while HBM handles the hottest data and high-frequency computation, reducing the repeated movement of model weights, KV cache, and retrieval data between the host and GPU.
UCIe is the most important industry signal in these specifications. With a unified processor interconnect, HBF can connect more flexibly to GPUs and CPUs, while the value chain expands beyond standalone NAND dies to logic base dies, advanced packaging, controllers, software scheduling, and system validation. Google and Tenstorrent joining the alliance indicates that customers are beginning to participate in defining the standard, rather than leaving storage vendors to make unilateral claims.
The maximum bandwidth of 3.0TB/s remains significantly below that of the most advanced HBM, but the maximum capacity of 512GB is far greater than that of a single HBM stack. HBF’s commercial value depends on usable bandwidth per dollar, resident capacity per watt, and the number of data movements—not on beating HBM in peak speed.
For SK hynix, HBF extends the company’s HBM-derived capabilities in stacking, TSV, and system collaboration into NAND, while creating a unified AI NAND narrative with its 10th-generation 375-layer 4D NAND and enterprise SSD roadmap. However, an initial standard does not mean revenue realization: customer validation, endurance, write amplification, software transparency, packaging costs, and mass-production yields remain critical disproof points over the next 2 to 4 years.
From “Does HBF Exist?” to “What Does HBF Look Like?”
In August 2025, SK hynix and Sandisk announced a partnership to advance HBF; in February 2026, they established a standardization working group under the Open Compute Project (OCP); by August 2026, the initial standard had defined specific capacity, bandwidth, interconnect, and packaging boundaries. Moving from the alliance’s launch to public specifications within six months was a relatively short timeline, indicating that industry discussions had shifted from conceptual feasibility to interface compatibility.
The released specifications contain three sets of key figures. First, capacity is capped at 512GB, using 8-layer and 16-layer NAND die stacks. Second, bandwidth is divided into three tiers, Grade 1 through Grade 3, spanning approximately 0.4TB/s to 3.0TB/s. Third, processor interconnects use UCIe, alongside definitions for electrical characteristics, stacking-process reliability and packaging guidelines, as well as software I/O principles.
Together, these parameters answer the first questions that the supply chain needs resolved: how high the dies must be stacked, what reliability requirements the package must withstand, which interface processors use for access, and how software identifies different performance grades. Once these boundaries are public, GPU, CPU, logic-chip, packaging, and system vendors can begin parallel development.
Key visual for the HBF standard specifications published by the SK hynix Newsroom on August 4, 2026.
HBF Addresses the High Cost of Data Movement, Not Insufficient Compute
During AI training, attention centers on GPU compute and HBM bandwidth; the challenges during inference are more complex. Model weights must remain resident, long contexts continuously expand the KV cache, and retrieval-augmented generation also requires access to vector databases and external knowledge. The more concurrent users there are, the more data must be retained and scheduled. Much of this data does not need to be read from HBM every clock cycle, yet cannot tolerate the high latency of the traditional SSD path through PCIe, host memory, and the operating system.
HBF seeks to fill precisely this gap. It brings NAND closer to the processor, delivering bandwidth through far greater parallelism than conventional SSDs while retaining NAND’s high capacity and low unit cost. Systems can keep the hottest tensors and caches in HBM, place warm data in HBF, and assign colder data to SSDs. HBF is a new tier in a “tiered memory” architecture.
Based on the official figures, although Grade 3’s maximum bandwidth of 3.0TB/s cannot replace the most advanced HBM, it already exceeds the performance range of traditional enterprise SSDs. More important is the 512GB capacity: if systems can access this capacity at reasonable latency, much of the data that previously had to be paged back and forth among host memory, SSDs, and GPUs could remain near the package for longer.
This would change the optimization objectives for AI infrastructure. The market has traditionally compared bandwidth per chip, but HBF is better assessed using three system-level metrics: effective bandwidth per dollar, accessible capacity per watt, and the amount of data moved to complete one inference. Provided that the reduction in data movement is sufficient to offset NAND access latency, HBF does not need to beat HBM in absolute speed to reduce total cost of ownership.
UCIe Turns a Storage Issue into a System-Platform Issue
The adoption of UCIe in these specifications has greater long-term significance than simply publishing bandwidth figures. UCIe is an open chiplet-interconnect specification designed to connect chiplets from different process nodes and vendors within a package. Connecting HBF to GPUs and CPUs through UCIe means that it is progressing from “a proprietary memory product from one vendor” toward a composable system component.
An open interface will broaden the pool of potential participants. NAND vendors provide the storage medium and stacking, logic-chip vendors handle control and error correction, advanced-packaging vendors address high-density interconnects and thermal management, GPU and CPU vendors determine coherency and access models, and cloud providers and software developers allocate model weights, KV cache, and retrieval data to the appropriate tiers. If any link is missing, the specifications can only remain at the sample stage.
Google and Tenstorrent’s participation in the alliance therefore warrants attention. Google owns models, cloud infrastructure, and internally developed accelerators, enabling it to derive capacity, bandwidth, and software requirements from real workloads; Tenstorrent represents a more open AI compute architecture. Their participation does not prove that HBF will be procured at scale, but it does show that the standards discussion has attracted processor and system customers, bringing it closer to a commercially viable loop than a unilateral roadmap announcement by storage vendors.
Why SK hynix Is Betting Simultaneously on HBM, HBF, and Enterprise SSDs
SK hynix’s competitive advantages have previously centered on HBM: high-bandwidth DRAM, TSV stacking, advanced packaging, and joint validation with leading GPU customers. HBF extends these capabilities into NAND at scale for the first time. Although NAND differs from DRAM in storage medium, endurance, and control mechanisms, organizational capabilities in high-layer stacking, logic base dies, thermal design, yield management, and system collaboration can be reused.
At the same FMS 2026 event, the company unveiled its 10th-generation 375-layer 4D NAND under development for the first time, stating that performance per watt had improved by 2.5 times versus the previous generation and that it planned to begin mass production of high-performance, high-capacity enterprise SSDs based on the technology in early 2027. This was not an exhibit unrelated to HBF: NAND with more layers and higher energy efficiency provides the material foundation for HBF to increase capacity density and control power consumption, while enterprise SSDs provide controllers, firmware, customer validation, and data-center channels.
This roadmap divides SK hynix’s AI storage portfolio into three tiers: HBM provides maximum bandwidth, HBF provides high capacity and high bandwidth near the package, and enterprise SSDs provide persistent storage at greater scale. The company has previously relied on HBM for high margins and customer stickiness; if HBF matures, it may shift NAND from a commodity product with greater price-cycle exposure toward a solution jointly defined with compute platforms.
This also represents an incremental addition to the existing investment framework. Previous assessments of SK hynix primarily focused on HBM4 order commitments, the 1c process, TSV capacity, and M15X expansion, while NAND was viewed mainly as a source of cyclical upside. With the HBF standard taking shape, NAND is beginning to gain a second structural growth narrative: rather than merely waiting for prices to rise, it can seek entry into the memory hierarchy of AI accelerators. At this stage, however, HBF revenue still cannot be treated as a source of certain earnings over the next two years, because considerable distance remains between standards, samples, platform validation, and mass production at scale.
Impact on the Supply Chain: Incremental Value Will Extend Beyond NAND Manufacturers
If HBF enters mass production, the most direct beneficiaries will be manufacturers with advanced NAND, stacking capabilities, and an established data-center customer base. SK hynix and SanDisk have taken the lead in establishing the standard, gaining an opportunity to define interfaces and validation methodologies; whether Samsung, Kioxia, Micron, and other manufacturers join or introduce compatible roadmaps will determine whether HBF can become a true industry standard.
The second layer of value lies in the logic base die and controller. NAND’s read/write latency, bad-block management, error correction, wear leveling, and write-amplification issues will not disappear through stacking. For processors to treat HBF as a predictable memory tier, control logic must provide more stable latency, stronger error correction, and more transparent software interfaces. High bandwidth will increase controller parallelism and logic complexity, potentially making the logic-chip content value significantly higher than in conventional NAND packages.
The third layer is advanced packaging and testing. Eight-layer and 16-layer stacking are not the end of the technical challenge; the real difficulty is simultaneously ensuring thermal stability, electrical integrity, and yield under high bandwidth, high power density, and large capacity. With HBF adopting UCIe, chiplet interconnects, packaging substrates, bonding, testing, and thermal management may all see incremental demand. However, equipment investment will precede mass-production revenue, so supply-chain companies must still await customer validation and orders rather than extrapolating capacity utilization solely from the publication of the standard.
The fourth layer is software. Tiered memory can deliver value only if scheduling is sufficiently automated. Developers will not want to decide manually for every model which data should reside in HBM, HBF, or SSD. Runtimes, compilers, and operating systems need to migrate data dynamically based on access frequency, latency sensitivity, and lifecycle. The greater the software transparency, the lower the adoption barrier for HBF; conversely, even strong hardware specifications may be held back by the cost and complexity of software modifications.
Commercialization Still Faces Five Hurdles
The first hurdle is media latency and endurance. NAND’s physical characteristics mean that it cannot handle all high-frequency writes like DRAM. HBF is best suited to read-intensive, capacity-sensitive workloads; if model inference continuously generates large volumes of random writes, write amplification and endurance management will erode its performance and cost advantages.
The second hurdle is effective bandwidth. 3.0TB/s is the specification ceiling, not the bandwidth applications can continuously obtain. Error correction, protocol overhead, access locality, thermal throttling, and controller scheduling will all reduce real-world performance. The most important metrics for future samples to disclose are not peak figures, but model-loading time, time to first token, long-context throughput, and performance per watt.
The third hurdle is packaging economics. HBF will have a clear role only if it is both cheaper than expanding HBM capacity and faster than the conventional SSD path. If the logic base die, advanced packaging, and cooling costs are too high, system vendors may choose more HBM, CXL memory, or optimized SSD caching.
The fourth hurdle is ecosystem compatibility. The open OCP specification reduces the risk of proprietary lock-in, but a true standard requires multiple suppliers, multiple processor platforms, and reproducible software stacks. The participation of Google and Tenstorrent is a starting point; the positions of leading GPU vendors, more cloud providers, and other NAND manufacturers will determine the market ceiling.
The fifth hurdle is mass-production yield. Sixteen-layer stacking concentrates more dies in a single package, and a defect in any individual layer may affect finished-product yield. SK hynix’s HBM stacking experience is an advantage, but it does not directly prove that NAND stacking, the logic base die, and the new interface can be mass-produced at sufficiently low cost.
How HBF, HBM, CXL Memory, and SSDs Will Divide Their Roles
To understand HBF’s market opportunity, large-capacity storage solutions cannot all be placed on the same speed ranking. HBM pursues maximum bandwidth and deterministic latency near the processor, making it suitable for frequently accessed model parameters, activations, and intermediate computational results; HBF sacrifices some latency and write capability in exchange for greater capacity near the package; CXL memory expands host-side DRAM pools through standard interconnects, with advantages in capacity sharing and server-level composability; enterprise SSDs handle persistent data at the lowest cost per unit of capacity. The four address data at different temperatures.
HBF has the greatest opportunity to penetrate two workload categories. The first is read-intensive, high-capacity model weights with access locality. Model parameters do not need to be rewritten as frequently as activations, making them suitable for placement in high-capacity media before hot data is transferred into HBM. The second is selected KV caches, vector indexes, and retrieval corpora used in long-context inference. These data need to respond faster than conventional SSDs, but may not justify permanently occupying expensive HBM.
Conversely, the large volume of gradient updates, random writes, and latency-sensitive workloads during training may not be suitable for HBF. Even if peak hardware bandwidth reaches 3.0TB/s, NAND programming and erase characteristics will still constrain write-intensive use cases. In its initial phase, HBF is more likely to supplement HBM capacity than replace general-purpose memory. If manufacturers blur this boundary to expand the market, real-world workload testing could readily expose performance shortfalls.
CXL is another important alternative. CXL memory can pool DRAM at the server-chassis or even rack level, while ecosystem maturity and software compatibility are improving. HBF’s advantages are closer proximity to the processor, greater packaging parallelism, and lower cost per unit of capacity; its disadvantages are media latency, endurance, and the difficulty of replacing packaged components. Ultimately, systems may use both: HBM for the hottest data, HBF for warm data near the package, CXL memory for shareable capacity, and SSDs for the persistence tier. The HBF market does not require other tiers to disappear; it only requires HBF to establish a stable role within this hierarchy.
Unit Economics Will Determine Whether HBF Is a Good Business
Following the publication of the standard, the market is most likely to overestimate capacity and underestimate logic and packaging costs. 512GB appears far higher than the capacity of a single HBM device, but an HBF package also requires control logic, error-correction resources, a UCIe interface, power management, and thermal design. If these non-NAND costs are too high, HBF’s total-cost advantage over “more HBM plus high-speed SSDs” will narrow materially.
For customers, the appropriate basis of comparison is neither price per GB nor peak bandwidth, but the total cost of completing a fixed inference task. This calculation must simultaneously account for accelerator idle time, server power consumption, HBM occupancy, model-loading time, request throughput, and data-center space. If HBF allows more models to remain resident near accelerators and reduces data movement across PCIe and networks, even a relatively expensive individual device may recover its cost by improving GPU utilization. The higher the hourly cost of a GPU, the greater the economic value of reducing idle time.
For SK hynix, earnings quality depends on whether HBF can escape the commoditized pricing of conventional NAND. An open standard will expand the market, but it will also reduce the likelihood of long-term exclusivity. The company needs to differentiate through the logic base die, packaging yield, customer co-design, and software support rather than relying solely on supplying NAND dies. If HBF ultimately becomes standardized media paired with a general-purpose controller, price competition may still revert to wafer costs and the race for higher layer counts; if it becomes a solution deeply integrated with GPU platforms, margins and order visibility may then more closely resemble the HBM business.
The distribution of value across the supply chain will also change accordingly. High-layer-count NAND provides capacity, but the controller determines effective performance, advanced packaging determines yield, and software determines whether customers actually use the product. NAND may account for a large share of device bill-of-materials cost, yet the incremental profit may not remain entirely with NAND manufacturers. Investment analysis must distinguish between “shipment growth” and “higher content value”: HBF will create structural profit, rather than merely consume more NAND wafers, only if customers are willing to pay a premium for improved system performance.
From Standard to Revenue: At Least Four Stages
The first stage is specification stabilization. The current first-edition standard has defined capacity, bandwidth, and interconnect boundaries; the next step is to disclose more detailed electrical parameters, error models, software interfaces, and consistency requirements. If the specification changes frequently, processor and packaging manufacturers will postpone investment.
The second stage is engineering samples. Samples must demonstrate sustained bandwidth, tail latency, power consumption, and endurance in real AI workloads rather than merely showing peak sequential-read performance. The most convincing data would include large-model loading time, time to first token, long-context throughput, the number of concurrent requests, and system-power savings relative to HBM-only or SSD-based solutions.
The third stage is platform validation. GPU, CPU, or dedicated AI-accelerator vendors need to complete UCIe interoperability, thermal design, and software adaptation. Cloud providers will typically also validate fault isolation, serviceability, and multi-tenant security. This stage may take longer than chip development because any system-level failure could affect expensive compute clusters.
Only the fourth stage brings revenue at scale. Even if samples emerge in the second half of 2026, mass-production revenue will still depend on platform launch schedules, customer capital expenditure, and supply-chain yields. If the market assumes margins comparable to a mature HBM business at the sample stage, it could easily overlook the time required for standards iteration and customer validation. A more reasonable approach is to increase the probability of revenue progressively at each milestone: publication of the specification proves only the direction, engineering samples demonstrate performance, platform design wins validate demand, and mass-production orders confirm the financial contribution.
What to Track Next
Over the next 12 months, three engineering milestones should be monitored first: whether OCP releases more comprehensive electrical and software specifications; whether SK hynix, SanDisk, or their partners deliver functional samples; and whether any GPU, CPU, or AI accelerator platform announces validation. Only when specifications, samples, and platforms form a complete loop will HBF move from a standards announcement to a product cycle.
The second set of indicators concerns real-world performance. The focus should not remain on peak bandwidth, but on the capacity, power consumption, read/write mix, latency distribution, and cost associated with each Grade. In particular, HBF should be compared with three alternatives—“more HBM,” “CXL memory,” and “high-speed enterprise SSDs”—on total cost of ownership under the same inference workload.
The third set of indicators concerns SK hynix’s execution. Whether 375-layer 4D NAND enters mass production for enterprise SSDs in early 2027 as planned, whether the NAND business can continue improving its product mix, and whether HBF receives dedicated capex and customer-validation disclosures will collectively determine when this new roadmap begins to appear in the financial statements.
At this stage, the most prudent investment conclusion is that HBF’s initial standardization has materially strengthened the credibility of SK hynix’s AI NAND strategy, but has not increased confidence in near-term earnings forecasts. It advances the company one step from an “HBM leader” toward a “tiered-memory platform supplier,” while expanding the competitive landscape from DRAM and NAND chips to interfaces, packaging, controllers, and software. The real catalyst for future re-rating will not be another announcement of a larger bandwidth figure, but customer platforms demonstrating at mass-production economics that 512GB of capacity can indeed reduce data movement in AI inference and deliver measurable improvements in power consumption, latency, and cost.