404K SEMI-AI Semiconductor Equipment Weekly — July 12, 2026 — WFE Upgrades, High-NA Adoption Divergence, and Testing and Cleaning Expansion
目录
Overall View This Week
Front-End Wafer Fabrication Equipment
Metrology, Inspection, and Testing
Advanced Packaging Equipment and Critical Materials
Company, Order, and Capital-Expenditure Validation
Divergences, Counterarguments, and Next Week’s Watchlist
Demand expectations for semiconductor equipment continued to rise this week. WFE of approximately $200 billion in 2027 has become the market consensus, with the debate shifting to whether it can reach $250 billion in 2028. Incremental front-end equipment demand is being driven jointly by advanced logic and memory. High-NA EUV, etch and deposition, cleaning, and process control should all benefit, although the timing is beginning to diverge. Earnings leverage in testing and advanced packaging equipment is also being reassessed, with Teradyne’s testing market, ASMPT’s logic TCB business, and Lam Research’s cleaning business providing three new signals. Valuations already discount much of the aggregate growth; the next phase will require orders, market share, and gross margins to identify which companies can genuinely outperform WFE.
404K SEMI-AI | 2026-07-12
Overall View This Week
The equipment upcycle remains intact, but the market has moved from asking whether growth exists to determining who can convert it into higher profits. Morgan Stanley raised its 2026–2028 WFE forecasts to $154.6 billion, $201.9 billion, and $227.3 billion. Citi’s trajectory is more optimistic at approximately $145 billion, $200 billion, and $250 billion, respectively. The two forecasts are closely aligned for 2027, with the main divergence centered on 2028.
The aggregate upside remains fundamentally supported, but pricing is contributing more than shipments. Global semiconductor sales rose 118.8% year over year and 16.1% month over month in May, above the historical average sequential increase of 8.5% for the period. Memory sales rose 325.7% year over year, with memory pricing contributing approximately two-thirds of the industry’s revenue growth year to date. Industrywide shipments declined 2.7% sequentially, while average selling prices rose 19.3%. Equipment orders therefore have a strong revenue backdrop, although the breadth of demand still requires monitoring.
Three structural changes matter most this week. First, the economics of High-NA EUV are beginning to diverge by die size, with DRAM potentially adopting the technology ahead of large logic chips. Second, incremental equipment demand is spreading beyond traditional lithography, etch, and deposition into cleaning, process control, testing, and advanced packaging. Third, valuations no longer reward WFE growth alone; gross margins, market share, and customer value are increasingly determining relative returns.
Stock selection is shifting from a broad rally in large equipment names to segment-level winners and losers. Morgan Stanley prefers MKS and Onto Innovation, where 2027 earnings power is not yet fully reflected, and remains constructive on KLA and Lam Research, while becoming less enthusiastic about large equipment stocks overall. KLA benefits from an expanding advanced-logic customer base; Camtek faces HBM share concerns; and Lam Research’s cleaning share gains provide a new growth source beyond etch and deposition.
Front-End Wafer Fabrication Equipment
High-NA EUV is more likely to be adopted first in DRAM because smaller dies do not require two-mask stitching. High-NA increases numerical aperture from 0.33 to 0.55 and improves resolution from approximately 13 nm to approximately 8 nm, theoretically increasing pattern density by roughly 2.8x. It can replace certain multiple-patterning processes with a single exposure, reducing masks, lithography–etch cycles, and opportunities for defects.
Half-field limitations defer the economic inflection point for large logic chips. One dimension of the High-NA exposure field decreases from approximately 33 mm to 16.5 mm. Large dies such as GPUs require stitching across two masks. Current throughput is 175 wafers per hour in AA mode and 135 wafers per hour in AB mode, a gap of approximately 23%. Based on 2025 estimates, High-NA exposure tool costs are approximately 2.4x those of low-NA EUV for small dies and approximately 3.1x for large dies. By 2030, improved availability and throughput could reduce these multiples to approximately 1.9x and 2.1x, respectively.
DRAM adoption could lead logic by approximately one to three years. Bernstein expects Samsung and SK Hynix to introduce High-NA at the 1d node in 2027, followed by Intel at its A14 node in 2028. Samsung Foundry and TSMC could adopt it around 2029 and 2030, respectively. Smaller DRAM dies make the economics of single-mask exposure easier to justify, while large logic chips must await further improvements in tool availability, stitching efficiency, and total process cost.
ASML benefits both from High-NA adoption and from its delay. Slower adoption would prompt customers to buy more mature low-NA EUV systems in the near term, which carry higher margins. Once High-NA is deployed, some value from etch, deposition, and cleaning steps shifts to lithography. Bernstein expects ASML’s overall lithography intensity to increase from 24% in 2025 to 26% in 2028, with EUV revenue reaching €42.7 billion and DUV revenue reaching €20.0 billion in 2030.
EUV capacity is a hard constraint on whether WFE growth can materialize from 2027 onward. Bernstein raised its 2027 EUV shipment forecast from 86 to 91 systems and expects shipments to reach 125 systems in 2030. JPMorgan believes that ASML guiding toward 90 EUV shipments in 2027 during its second-quarter results would be only modestly positive. A range of 90–100 systems, combined with signals of additional capacity beyond 2028, would be required to support a stronger rerating.
Etch, deposition, and cleaning still offer growth, but competition is shifting toward the ability to integrate adjacent processes. Beyond etch and deposition, Lam Research increased its cleaning market share from 13% in 2022 to 24% in 2025, a gain of approximately 1,000 basis points. Cleaning intensity has remained at 5%–6% of the semiconductor equipment market over the long term, meaning the segment itself may not outperform WFE. Lam can nevertheless continue gaining share through backside power delivery in advanced logic, synergies with etch and deposition, and wet processing for advanced packaging.
Cleaning represents a market-share opportunity, not a new aggregate supercycle. Cleaning accounts for approximately 10% of Lam Research’s product mix, and the company estimates an opportunity of approximately $1 billion related to advanced logic and advanced packaging. This is not yet large enough to reshape the income statement on its own, but it demonstrates that Lam’s growth sources are broadening. Investors should monitor tool qualifications at leading logic customers, panel-level packaging orders, and cleaning market share rather than WFE alone.
Metrology, Inspection, and Testing
The addressable market for test equipment may offer more upside surprise than front-end WFE. Historically, the median semiconductor test market has equaled approximately 8.3% of WFE. By segment, SoC testing represents approximately 12.1% of non-memory WFE, while memory testing represents approximately 3.8% of memory WFE. If WFE exceeds $250 billion in 2028, historical intensity implies a test market of approximately $21 billion. This would exceed Teradyne management’s medium-term outlook of $12 billion–$14 billion and UBS’s previous forecast of $14.8 billion.
Chip complexity and test intensity are the key variables for the test market; front-end capacity expansion is only the starting point. If advanced logic, chiplets, and high-bandwidth memory increase test duration and coverage requirements, test revenue could grow faster than wafer capacity. Conversely, if customers reduce unit test time through parallel testing, test-program optimization, or higher equipment utilization, historical intensity would overstate the market opportunity. Whether Teradyne can maintain approximately 40% market share is more important to monitor than WFE forecasts alone.
Process control continues to benefit from an expanding advanced-logic customer base, while HBM metrology share is diverging. Morgan Stanley raised KLA’s valuation multiple because its advanced-logic customer base is expanding from a single industry leader to Intel, Rapidus, and potential new projects. The case for higher metrology and inspection intensity at Nova remains intact, but the market is beginning to question whether the company can continue outperforming WFE in 2027. Camtek’s target multiple was reduced because of HBM share risks relative to Onto Innovation and KLA.
Outcomes for metrology and inspection companies depend on the value of yield improvement, not the number of tools sold. Customers are willing to pay for faster defect identification and earlier yield improvement, which is why process-control companies can sustain high gross margins. Expansion among advanced-node customers, greater process-control intensity in DRAM, and HBM packaging yields are positive variables. Improved in-house inspection capabilities, adoption of competing tools, and delays to individual projects are counterarguments.
Advanced Packaging Equipment and Critical Materials
Advanced packaging equipment is seeing a combination of strong logic demand, slower HBM momentum, and simultaneous PCB capacity expansion. Morgan Stanley expects OSAT capital expenditure to grow 45% in 2026, above its previous estimate of 34%, while PCB-company capital expenditure is expected to rise approximately 69%. ASMPT’s Semiconductor Solutions and SMT businesses should therefore both benefit, although logic TCB orders are stronger while HBM-related TCB equipment orders remain slower.
Logic TCB currently offers greater order visibility than HBM TCB. TSMC’s CoWoS capacity is expected to reach 200,000 wafers per month by the end of 2027, and ASMPT is the sole supplier of TCB equipment for CoWoS-L substrates. HBM also uses TCB, but when server DRAM margins are higher, memory manufacturers may prioritize DRAM dies for server products, temporarily slowing HBM equipment purchases. Key indicators include chip-to-wafer TCB orders, adoption by HBM customers, and book-to-bill ratios.
ASMPT’s second growth driver comes from SMT and PCB capital expenditure. The company’s SMT sales have historically shown a strong correlation with capital expenditure by PCB manufacturers, while AI-related PCB capacity expansion provides cyclical leverage for its traditional surface-mount business. Morgan Stanley expects Semiconductor Solutions and SMT revenue to grow 30% and 27%, respectively, in 2026 and raised its 2026–2028 EPS forecasts by 7%, 10%, and 10%.
